Design & Technology of Integrated Systems 2015
21.-23.04.2015, Naples, Italy
D. Noll, U. Schwalke
Silicon CMOS compatible in-situ CCVD growth of graphene on silicon nitride
Abstract – In this paper we report on the possibility of the silicon CMOS compatible fabrication of graphene ﬁeld effect transistors on a silicon nitride high-k dielectric. For this purpose the catalytic chemical vapor deposition, which has already been approved to work on SiO2 surfaces, is used to grow the graphene. First electrical results indicate a bilayer graphene with an on/off current ratio of 103 to 104, which can be achieved with lower threshold voltages. A greater on/off current ratio may be possible, as the off current is determined through gate leakage current.
Member of the Technical Programm Committe: Prof. Dr. U. Schwalke
Inaugural talk of Ilke Ercan
Date: Friday, 17.04.2015, 14:00 c.t.
Place: S2|17 103
Speaker: PhD Ilke Ercan
Heat Dissipation Bounds for Nanocomputing: Methodology and Applications
Heat dissipation and power consumption are the critical challenges facing the realization of emerging nanocomputing technologies. There are different components of this dissipation, and a part of it comes from the unavoidable cost of implementing logically irreversible operations. This stems from the fact that information is physical and manipulating it irreversibly requires energy. The unavoidable dissipative cost of losing information irreversibly fixes the fundamental limit on the minimum energy cost for computational strategies that utilize ubiquitous irreversible information processing.
A relation between the amount of irreversible information loss in a circuit and the associated energy dissipation was formulated by Landauer's Principle in a technology-independent form. In a computing circuit, in addition to the information-theoretic dissipation, other physical processes that take place in association with irreversible information loss may also have an unavoidable thermodynamic cost that originates from the structure and operation of the circuit. In conventional CMOS circuits such unavoidable costs constitute only a minute fraction of the total power budget, however, in nanocircuits, it may be of critical significance due to the high device density and operation speeds required. The lower bounds on energy, when obtained by considering the irreversible information cost as well as unavoidable costs associated with the operation of the underlying computing paradigm, may provide insight into the fundamental limitations of emerging technologies. This motivates us to study the problem of determining heat dissipation of computation in a way that reveals fundamental lower bounds on the energy cost for circuits realized in new computing paradigms.
In this talk, I present a physical-information-theoretic methodology proposed to obtain such bounds for the minimum energy requirements of computation for concrete circuits realized within specific paradigms, and demonstrate its application via prominent nanocomputing proposals. I discuss the unavoidable heat dissipation problem and emphasize the significance of limitations it imposes on emerging technologies, present the methodology developed to obtain the lower bounds on the unavoidable dissipation cost of computation and demonstrate our methodology via its application to various non-transistor-based (e.g. QCA) and transistor-based (e.g. NASIC) nanocomputing circuits. I also employ two CMOS circuits, in order to provide further insights into the application of our methodology by using this well-known conventional paradigm. I expand this methodology to modularize the dissipation analysis for QCA and NASIC paradigms, and discuss prospects for automation. Finally, I comment on the role of fundamental lower bounds in technology assessment for determining the trends in nanoelectronic computing.