226th Meeting of the Electrochemical Society
05.-10.10.2014, Cancún, Mexico
The ISTN participates with three presentations in the 226th Meeting of the Electrochemical Society.
Symposium Q1: Emerging Nanomaterials and Devices
T. Krauss, F. Wessely, U. Schwalke
Novel electrostatically doped planar field-effect transistor for high temperature applications
Abstract – In this paper, we investigate by simulation and by evaluation of experimental data the feasibility of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect-transistor (FET) structure which is based on our already published Si-nanowire (SiNW) technology. The key technology for this dual-gated general purpose FET contains Schottky S/D junctions on a silicon-on-insulator (SOI) platform. In combination with electrostatic doping and a dual-gate configuration, the Schottky junctions significantly increase the temperature robustness of the device.
Symposium M1: Nanocarbon Fundamentals and Applications – from Fullerenes to Graphene
M. Keyn, U. Schwalke
Highly parallelized carbon nanotubes for field-effect device applications
Abstract – In this work we report on a custom made contact layout which utilizes large scale parallelization of in situ grown carbon nanotubes (CNTs). If parallelization of CNTs is adapted to a carbon-silicon-hybrid technology for producing field-effect devices, it is for example possible to increase the on-state current of a field-effect transistor. The effect can be compared to increasing a transistor’s gate width in conventional silicon technology.
U. Schwalke, P.J. Wessely
Improved bilayer graphene transistors for applications in nanoelectronics
Abstract – In this contribution we report on an improved method to fabricate bilayer graphene transistors (BiLGFETs) transfer-free directly on oxidized silicon wafers in a silicon-CMOS compatible fabrication process. By means of catalytic chemical vapor deposition (CCVD) the BiLGFETs are realized directly on oxidized silicon substrate without transfer. These BiLGFETs possess unipolar p-type device characteristics with a high on/off-current ratio between 1•105 and 1•107 at room temperature exceeding previously reported values by several orders of magnitude. In order to improve device performance, an additional fabrication step has been developed, by which means the contact resistance is lowered by more than a factor of 10.
SBMicro 2014 – 29th Symposium on Microeletronics Technology and Devices
01.-05.09.2014, Aracaju, Sergipe, Brazil
V.B. Sivieri, P.J. Wessely, U. Schwalke,
P.G.D. Agopian, J.A. Martino
Graphene for advanced devices applications
Abstract – In this work, the behavior of the different types of graphene transistors in relation to the number of stacked layers are investigated as well as the influence of a palladium layer deposited on the pads of a CCVD grown graphene FET. The advantages of using this material in Tunnel FETs are also discussed. Bilayer graphene FETs with high on/off-current ratio, in the order of 106 were found. In contrast to bilayer graphene, monolayer graphene cannot be used in logical electronics applications, once that their on/off-current ratio is very low.
Nanoelektronik-Kolloquium mit Andreas Kerber
Termin: Freitag, 22.08.2014, 14:00 c.t.
Ort: S2|17 103
Referent: Dr.-Ing. Andreas Kerber
Characterization of BTI induced variability in scaled metal gate / high-k CMOS technologies
Abstract – Time-zero and time dependent variability is a growing concern for aggressively scaled transistor technologies with metal gate/high-k stacks. Bias temperature instability (BTI) in PMOS as well as NMOS devices is considered the most dominant time dependent variability component and needs to be modeled using stochastic processes. The physical nature of the stochastic process is still under debate and to support the model development efforts large statistical data sets are essential. In this presentation, we will focus on the characterization challenges related to stochastic BTI process in small area CMOS devices and discuss the large scale data we collected on discrete SRAM and logic devices. Finally we will elaborate on the impact of BTI induced variability on End-of-Life threshold voltage distributions and show that BTI induced variability is not the major contributing factor in the post stress threshold voltage variability in planar metal gate/high-k CMOS devices.
Design & Technology of Integrated Systems 2014
06.-08.05.2014, Santorini, Greece
ISTN participates with three presentations in this year's International Conference on Design & Technology of Integrated Systems in the Nanoscale Era.
Session NS2: New Technologies
Session Chair: Prof. Dr. U. Schwalke
T. Krauss, F. Wessely, U. Schwalke
An electrostatically doped planar device concept
Abstract – In this paper, we propose and demonstrate by simulation an electrostatically doped and therefore voltageprogrammable planar field-effect-transistor (FET) structure which is based on our results of already published Si-nanowire (SiNW) devices. The key technology for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-oninsulator (SOI) platform. The desired transistor type, i.e. NFET or PFET, is selectable on the fly by applying an appropriate control-voltage which significantly enhances flexibility in design of integrated circuits.
M. Keyn, A. Kramer, U. Schwalke
Dependence of annealing temperature on cluster formation during in situ growth of CNTs
Abstract – In this work we use atomic force microscopy to investigate the inﬂuence of the annealing temperature on the formation of nano-clusters in our growth technique for carbon nanotubes. Cluster formation is carried out just before in situ growth of carbon nanotubes from a methane feedstock by means of catalytic chemical vapor deposition where the clusters act as the catalyst. Since cluster size and distribution are directly connected to diameter and amount of the grown carbon nanotubes, respectively, the cluster formation process is of great interest.
P. J. Wessely, U. Schwalke
2nd generation bilayer graphene transistors for applications in nanoelectronics
Abstract – In this paper we report on in-situ CCVD grown bilayer graphene transistors (BiLGFETs) in a Silicon-CMOS compatible fabrication process. By means of catalytic chemical vapor deposition (CCVD) the BiLGFETs are realized directly on oxidized silicon substrate without transfer. These BiLGFETs possess unipolar p-type device characteristics with a high on/off-current ratio between 1x105 and 1x107 at room temperature. At this stage, the maximal on-state current of a BiLGFET is clearly influenced by the contact resistance. In order to improve the performance of the produced BiLGFETs, an advanced fabrication step has been developed, by which means the contact resistance is lowered by a factor of 10.
Member of the Technical Programm Committe: Prof. Dr. U. Schwalke