40th IEEE Semiconductor Interface Specialists Conference
03.-05.12.2009, Arlington, VA, USA
R. Endres, T. Krauss, F. Wessely, U. Schwalke
Gentle Gate Last Process Integration of TiN/Gd2O3/Si MOS Capacitors and Field Effect Transistors
International Conference on Signals, Circuits & Systems 2009
06.-08.11.2009, Jerba, Tunisia
- Prof. Dr. Slim Boumaiza (Kanada)
- Prof. Dr. Udo Schwalke (IHT)
Organisation Special Session,
Metal Gate Electrodes And High-K Rare Earth Oxides For Future CMOS Applications:
- Dr. Heiner Gottlob (AMO)
- Ralf Endres (IHT)
F. Wessely, R. Endres, U. Schwalke
Down-Scaling of the Damascene Metal Gate Integration Process via Electron Beam Lithography
Abstract – Damascene-Metal-Gate technology gives rise to the implementation of crystalline gate dielectrics into modern MOS devices. Evaluation of the scalability of this fabrication process is important for a latter use in industrial-scale fabrication. Devices were processed on ultrathin Unibond SOI-Wafers. A specially designed layout with was patterned onto the substrates via mix and match electron-beam / UV lithography. A gate length of ~100 nm was chosen for a first approach. Reactive ion etching was performed for dummy gate and active area formation. Subsequently the surface was planarized via chemical mechanical planarization (CMP). In the following the dummy gate was removed, and on one hand replaced by molecular beam epitaxially grown crystalline gadolinium oxide (Gd2O3) and on the other with thermally grown SiO2 as reference material. Palladium was used as source/drain- and gate-metallisation. Atomic force microscopy and scanning electron microscopy were carried out for process monitoring. Especially the dummy gate formation, subsequent CMP and cleaning processes, as well as the dummy gate removal and the conformity of the replacement gate stack are of particular interest.
R. Endres, T. Krauss, F. Wessely, U. Schwalke
Damascene Metal Gate Technology for Damage-free Gate-Last High-K Process Integration
Abstract – In this work, we present MOS capacitors and MOS transistors with a crystalline gadolinium oxide (Gd2O3) gate dielectric and metal gate electrode (titanium nitride) fabricated in a replacement gate process. Since rare earth oxides as Gd2O3 are stable on silicon substrates and does not need a SiO2 interfacial layer (IFL), they are promising candidates to replace hafnium/zirconium based high-k gate dielectrics and are able to exceed the EOT = 0.8 nm frontier in future CMOS applications.
However, rare earth oxides are sensitive to high temperatures (e.g. after S/D anneals) and reactive ion etching. Therefore we have integrated crystalline high-k materials into a gentle damascene metal gate process by means of chemical mechanical planarization (CMP). Since the full damascene metal gate process is more time-consuming, we investigate various gate stacks on MOS-Cap level first and select the most promising candidates for MOSFET fabrication.
Initial results on ALD-TiN/Gd2O3/Si gate stacks on p- and n-substrates with equivalent oxide thicknesses (EOT) of 3.0 nm and 1.5 nm, respectively, are presented in this work.
216th Meeting of The Electrochemical Society
04.-09.10.2009, Vienna, Austria
U. Schwalke, L. Rispal
Carbon Nanotube Memory Devices: Mass-Fabrication and Electrical Characterization
6th International Symposium on Advanced Gate Stack Technology
22.-26.08.2009, San Francisco, USA
R. Endres, T. Krauss, F. Wessely, U. Schwalke
Damascene TiN-Gd2O3-Gate Stacks: Gentle Fabrication and Electrical Properties
Abstract – In this work, we present MOS capacitors with a crystalline gadolinium oxide (Gd2O3) gate dielectric and metal gate electrode (titanium nitride). Since rare earth oxides are stable on silicon substrates and do not need a SiO2 interfacial layer (IFL), they are promising candidates to replace hafnium/zirconium based high-k gate dielectrics and are able to exceed the EOT = 0.8 nm frontier in future CMOS applications. However, rare earth oxides are sensitive to high temperatures (e.g. after S/D anneals) and reactive ion etching. Therefore we have integrated crystalline high-k materials into a gentle damascene metal gate process by means of chemical mechanical planarization (CMP). Since the full damascene metal gate process is more time-consuming, we investigate various gate stacks on MOS-Cap level first and fabricate MOSFETs with the most promising candidates. In this work, we present initial results on TiN/Gd2O3/Si MOS capacitors with EOTs of 3.0 nm and 1.5 nm respectively.
8th Symposium Diagnostics & Yield
Advanced Silicon Devices and Technologies for ULSI Era
22.-24.06.2009, Warsaw, Poland
Nano-Electronics: From Top-Down to Bottom-Up?!
Abstract – Like no other technology, integrated silicon electronics has changed our daily life during the past 50 years. Integrated circuits (ICs) have become the indispensable resource of the modern knowledge based society: Without ICs, the rich multimedia experience we enjoy when using the internet, mobile phones or digital video and audio would not have been possible. This tremendous progress is based primarily on one major development: The continuous miniaturization.
Today, micro-electronics is in the transition to nano-electronics and device structures are as small as a virus, i.e. less than 100 nm. As lateral device dimensions are scaled down, the gate oxide thickness has to decrease accordingly. In fact, down-scaling of gate dielectric thickness is still a major challenge. To continue with down-scaling, new gate stack materials, like high-k dielectrics, have been introduced. Nevertheless, it is obvious that the traditional top-down technologies are becoming more and more impractical with the nanoscale.
Beyond the Moore's law era of silicon-CMOS, new bottom-up methods will be mandatory to implement e.g. low-dimensional semiconductor nanostructures, like carbon nanotubes (CNTs) which offer unique possibilities such as extremely low power dissipation, high surface sensitivity and low fabrication cost. However, until recently, fabrication methods of CNT-devices are very time-consuming and are not suitable for mass-fabrication.
This contribution will emphasize on emerging semiconductor technologies for nano-electronic applications. In particular, a novel approach for mass-fabrication of carbon nanotube field-effect transistors (CNTFETs) with high on/off ratio will be presented. The in-situ fabrication method is fully silicon-CMOS compatible and several thousand CNT-devices have been realized which may be used for logic and memory applications and sensors as well. The impact of this promising technological development and future challenges towards a CNT-silicon hybrid nanotechnology will be discussed.
Impressionen vom TUDay am 07.05.2009 aus dem Institut für Halbleitertechnik und Nanoelektronik und dem Hans-Busch-Institut. weiter
Impressionen von der Science-Tour NEnA am 22.03.2009
Besuch des Kanzlers
Impressionen vom Besuch des Kanzlers der Technischen Universität Darmstadt, Dr. M. Efinger, am 13.03.2009.
14th European Test Symposium
72. Jahrestagung der Deutschen Physikalischen Gesellschaft
25.-29.02.2008, Berlin, Germany
- Said Hamdioui – TUDelft, the Netherlands
- Simona Pappalardo – ST Microelectronics, Italy
- Tom Williams – Synopsys, US
- Gil Balog – OptimalTest, Israel
- Brady Benware – Mentor Graphics, US
- Srikanth Venkataraman – Intel, India
- Teresa McLaurin – ARM, US
- Udo Schwalke, ISTN, TU-Darmstadt, Germany
Yield, Reliability, and Variability in the Nano-Era: Will Existing Approaches Survive?
Abstract – It is widely recognized that variability in device characteristics and the new failure mechanisms in the nano-technology era will severely impact the design, manufacturing, and testing of future chips. In addition, time-to-market and time-to-volume pressure have created major engineering challenges in rapid yield learning and guaranteeing the required quality and reliability. The panel aims at gathering opinions on the different ways to deal with these challenges in order to survive the nano-era. Can we still rely on test data analysis to accurately predict the reliability of the manufactured chips? Can today's methodologies such as burn-in still be able to provide the required reliability? Can statistics provide the necessary information of the root cause of yield loss without performing the time-consuming physical failure analysis? Are existing test approaches still able to deliver the required product quality even if the failure mechanisms are shifting from permanent faults to intermittent and transient faults? Does the impact on memory differ from the impact on logic?
Deutsche Gesellschaft für Materialkunde
Arbeitskreistreffen Atomic Layer Deposition
20.02.2009, Berlin, Germany
Damascene metal gate technology: A solution to high-k gate stack challenges?
Abtract – Since the late 1960s, the normal fabrication method of CMOS transistors is known as the “gate first” approach. As the name indicates, gate dielectric and gate electrode are made first, i.e. prior to the self-aligned formation of the source (S) and drain (D) junctions by ion-implantation. As long as the gate stack has been made out of polycrystalline silicon and silicon dioxide, process integration was not an issue. Both materials are able to withstand high annealing temperatures and are compatible with reactive ion etching. However, after introducing novel gate stack materials, like high-k gate dielectrics and metal gate electrodes, the situation has been changed completely. These new materials are sensitive and degrade during high-temperature processing. In order to circumvent process-induced gate-stack damage, we have developed a “gate last” process flow, in which the self-aligned gate stack is made after S/D junctions. For the first time, fully functional metal gate MOSFETs with crystalline high-k dielectric have been fabricated by means of chemical mechanical polishing (CMP). Electrical results and details of the “gentle” damascene metal gate technology will be presented. To which extent the “gate last” approach is a general solution to the high-k metal gate challenges will be discussed.
Hochschul- und Berufsinformationstag 2009
Impressionen vom Hochschul- und Berufsinformationstag am 27.01.2009. weiter