11th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors
27.-28.11.2008, Veldhoven, Netherlands
R. Endres, F. Wessely, U. Schwalke
CMP-based Gate-Last High-K Integration
Abstract – Ever increasing gate leakages through ultra-scaled SiO2 gate dielectrics have led to extensive investigation of alternative materials with higher dielectric permittivity (high-K) in order to extend the unprecedented growth of IC complexity of the last four decades into the future. However, high temperature annealing and aggressive RIE was found to degrade the initial quality of the sensitive high-K gate stack. In order to minimize process induced oxide damage, we have integrated high-K dielectrics into a “gentle” damascene metal gate technology by means of chemical mechanical planarization (CMP).
As a universal platform, the replacement gate technology provides the possibility of investigations of various gate dielectrics, metal gate materials and substrates and their combinations directly at the device level.
L. Rispal, F. Wessely, U. Schwalke
Self aligned fabrication process for carbon nanotube based field-effect devices: transistors, memory cells and bio-sensors
Abstract – Carbon nanotube field-effect transistors (CNTFETs) are well recognized to become a possible replacement of the traditional MOSFET in the CMOS technology to develop logic circuits, so that Moore´s law can still be followed in the future. However, mass production should be possible for integration on a very large scale, i.e., billions of transistors on one wafer. We present in this work our new fabrication process for single-walled carbon nanotube (SWNTs) based devices. The process is based on chemical vapor deposition growth of the nanotubes using a sacrificial catalyst. SWNTs are grown directly on their final place avoiding any manipulations. Furthermore, only one-step lithography is necessary, not only in order to contact the devices but also to passivated them simultaneously. Polymethyl methacrylate (PMMA) is used as a passivation layer to protect the SWNTs from ambient air and increase the life time. Thanks to this suitable process, we have already fabricated around 15.000 passivated devices. Moreover, we show that our CNTFETs are suitable for memory applications. They can be used as non-volatile memory cells operating at room temperature. The memory function is obtained by the threshold voltage shift due to the highly reproducible hysteresis in the transfer characteristics. The ratio of the current levels between a logical “1” and a “0” is about 106. Lastly, CNTFETs are ideally suitable for biomedical sensor applications due to their excellent inherent properties such as ultra small size, high specific surface area, extremely high sensitivity and the above mentioned hysteresis effect. For example, the detection and identification of single viral particles may be possible using functionalized CNTFETs as sensors: The binding of a virus to a suitably functionalized semiconducting SWNT will measurably affect the gate-dependent electrical current-voltage characteristics of the transistor via charge transfer between the SWNT and the virus.
International Conference on Signals, Circuits & Systems 2008
07.-09.11.2008, Hammamet, Tunisia
214th Meeting of The Electrochemical Society
12.-17.10.2008, Honolulu, Hawaii
U. Schwalke and L. Rispal
Mass-Fabrication of Voltage-Programmable Non-Volatile Carbon Nanotube Memory Devices
Abstract – In this contribution we report on mass-fabrication of carbon nanotube field-effect transistors (CNTFETs) with high on/off ratio to be used as non-volatile memory cells operating at room temperature. Several thousands of memory devices have been realized using a complete insitu fabrication method. The storage of binary data in memory units is a fundamental prerequisite in information technology. Molecular memory devices with semiconducting singlewalled carbon nanotubes (s-SWNTs) are promising candidates to realize ultra-dense non-volatile memory cells . However, present state-of-the-art fabrication methods of CNTFETs are very time-consuming and are not suitable for fabrication of memory chips with millions of transistors. Our novel fabrication method allows growing of individual SWNTs directly within the desired device area. No tedious manual manipulation and alignment of the SWNTs is necessary. The self-aligned fabrication process allows mass-production of SWNT memory devices with high yield. Statistical analysis on hundreds of electrical measurements reveals that 71% of the devices are working (i.e. there is current between source and drain) and 67% of them show excellent semiconducting behavior (on/off ratio 106). 27% of the working devices have also a s-SWNT as the channel but with a small band-gap and only 6% of the working devices show a purely metallic behavior (i.e. no field-effect notable). The memory function is obtained by the threshold voltage shift (memory window) due to the highly reproducible hysteresis in the transfer characteristics. The ratio of the current levels between a logical “1” and a logical “0” is about 106. The “0” and “1” current levels are seen to be temporally stable and stay within the same decade. Long term data retention for more than 12 hours was also observed even at power off. More detailed measurements on data retention are in progress. Also, excellent endurance properties have been obtained after performing multiple read/write cycles. The reading current remains at the same level and depends only on the programming gate voltage applied before. Since the current levels do not depend on the previous history of read/write cycles and due to the long retention time, voltage-programmable CNTFETs have the characteristics of non-volatile memory cells. Since the process is silicon CMOS compatible, it opens the possibility to fabricate circuits, either by structuring a top gate on the in-situ grown SWNTs or by using buried isolated bottom-gate on SOI wafers to realize high density embedded or stand-alone memory units.
 S. Wang, P. Sellin, Appl. Phys. Lett. 87, 133117 (2005)
 L. Rispal et al., Jap. J. Appl. Phys. 47, 3287 (2008)
50 Jahre Microchip = 50 Jahre erfolgreiche Halbleitertechnik
Vor 50 Jahren stellte der Ingenieur Jack Kilby den ersten integrierten Schaltkreis vor…
… und heute kommt kaum ein technisches Produkt ohne Halbleitertechnik aus.
Das Institut für Halbleitertechnik der TU Darmstadt ist stolz darauf, seit 29 Jahren mit richtungweisenden Forschungsarbeiten in diesem Fachgebiet weltweit vertreten und anerkannt zu sein.
gez. Prof. Udo Schwalke,
Darmstadt, 12. September 2008
Projekttreffen BMBF-Verbundprojekt MEGA EPOS
Impressionen vom Projekttreffen des BMBF-Verbundprojekts MEGA EPOS am 07. und 08.07.2008.
3rd International Conference “Smart Materials, Structures and Systems”
08.-13.06.2008, Acireale, Sicily, Italy
Field-effect controlled single-walled carbon nanotube devices for biomedical sensor applications
Abtract – In this contribution we present a novel method for the realization of carbon nanotube field-effect sensors (CNTFESs) which will most likely have a strong impact on the next-generation of bio-sensors. CNTFESs are ideally suitable for biomedical sensor applications due to their excellent inherent properties: The response times of CNT-sensors are at least one order of magnitude faster than those based on solid-state sensors. CNT-based nano-sensors have the advantages that they are thousands of times smaller than even MEMS sensors. They consume much less power and have a high specific surface area leading to extremely high sensitivity. Therefore, CNTFESs are highly suitable as implantable sensors. The proposed CNTFESs are based on carbon nanotube field-effect transistors (CNTFETs) which are optimized for sensor applications. We have succeeded to develop a simple, reproducible fabrication process to grow individual CNTs and CNT-networks directly within the specified device area. No tedious manual manipulation and alignment of the CNTs is necessary. The method is suitable for mass-production. Electrical results of the fabricated fully functional CNTFETs are presented and the use of these devices as CNT-based field-effect controlled sensors for virus detection will be discussed.
213th Meeting of The Electrochemical Society
18.-23.05.2008, Phoenix, Arizona, USA
Design & Technology of Integrated Systems 2008
Special Session on Carbon Nanotube Transistors: Characterization, Compact Modelling and Circuit Design
25.-28.03.2008, Tozeur, Tunisia
Carbon Nanotubes Field Effect Transistors (CNTFET) are one of the most promising candidates for future nanoelectronics because of their unique one-dimensional geometry giving them excellent transport properties. It is possible to obtained a ballistic transport over 1µm at room temperature in the on state. This special session proposes an overview of their principle of operation, their characterisation, their compact models and their potential circuit performances.
Five papers are proposed (Conference Booklet):
- Structural and electrical characterization of CNTFETs fabricated by novel self-aligned growth method,
L. Rispal, U. Schwalke,
Institute for semiconductor Technology and Nanoelectronics, Darmstadt, Germany
- Double gate barrier CNTFET compact model,
J. Goguet, S. Fregonese, C. Maneux, T. Zimmer,
IMS Bordeaux, France
- Schottky barrier CNTFET compact model,
M. Najari1,2, S. Fregonese1, C. Maneux1, T. Zimmer1, N. Masmoudi2, H. Mnif2,
(1 IMS Bordeaux, France, 2 LETI, Tunisia)
- Dynamically Reconfigurable Logic Gates using CNTFET,
J. Liu, I O'Connor, D. Navarro, F. Gaffiot,
INL Lyon, France
- Mixed analog-digital design of a learning cell based on CNTFET for neuronal architectures,
M. He, J-O. Klein, E. Belhaire,
7th International Semiconductor Technology Conference
15.-17.03.2008, Shanghai, China
R. Endres, U. Schwalke
Damascene Metal Gate Technology for Damage-Free High-k Process Integration
Abtract – Many material systems are currently under consideration as potential replacements for the conventional SiO2 gate dielectric for future metal-oxide-semiconductor technology. The most promising candidates are high-k rare-earth metal oxides . However, high temperature annealing, aggressive reactive ion etching and post-gate cleaning during conventional transistor fabrication were found to degrade the initial quality of the sensitive high-k gate stack . In order to minimize process induced oxide damages (PIODs), we have integrated crystalline high-k dielectrics into a virtually damage-free damascene metal gate process. The leakage behavior of single high-k layers on blank and pre-structured Si-wafers before and after electrical stress has been probed using conductive atomic force microscopy (C-AFM). We have fabricated damascene metal gate MOS devices with different high-k gate dielectrics (gadolinium oxide (Gd2O3), lanthanum oxide (La2O3) or hafnium oxide (HfO2)) and various metal gate electrodes (tungsten (W), aluminum (Al), palladium (Pd) and platinum (Pt)). Electrical device characterization has been performed with the focus on (high-) temperature stability and leakage mechanisms. MOSFETs with gadolinium oxide (Gd2O3) gate dielectric and a tungsten (W) metal gate electrode has been fabricated in a gentle process by means of a damascene metal gate technology. Since high-temperature annealing and reactive ion etching are performed prior to gate stack deposition and the high-k layer is completely encapsulated against aggressive post-gate cleaning steps by the CMP-defined metal gate electrode, the initial quality of the high-k layer will be largely preserved. The fabricated devices are fully functional and show proper transistor behavior. To conclude, the proof-of-concept of the advanced process technology has been successfully demonstrated, which provides a solid base for further gate stack optimization, including dual-workfunction metal gate technology.
 G. D. Wilk, et al., Journal of Applied Physics, 89, pp. 5243-5275, 2001
 S. B. Samavedam, et al., IEDM, p.307, 2003
72. Jahrestagung der Deutschen Physikalischen Gesellschaft
25.-29.02.2008, Berlin, Germany
Artikel im Darmstädter Echo vom 15.02.2008
Aus der Wissenschaft
Richtungsweisende Chip-Schmiede am Park:
An der TU Darmstadt werden heute die Computer-Bausteine von morgen entwickelt
Obwohl Halbleiter zu Gegenständen des täglichen Lebens geworden sind, können nur wenige Menschen mit dem Begriff etwas anfangen. Forscher des Instituts für Halbleitertechnik der TU Darmstadt arbeiten daran, die Technologie noch leistungsstärker zu machen. weiter
International Conference on Biomedical Electronics and Devices
28.-31.01.2008, Funchal, Madeira, Portugal
Novel Field-Effect Controlled Single-walled Carbon Nanotube Network Devices for Biomedical Sensor Applications
Abtract – In this position paper we propose a novel method for the realization of carbon nanotube field-effect sensors (CNTFESs) which will most likely have a strong impact on the next-generation of sensors. CNTFESs are ideally suitable for biomedical sensor applications due to their excellent inherent properties such as ultra small size, high specific surface area and extremely high sensitivity. CNTFESs are based on carbon nanotube field-effect transistors (CNTFETs) which are optimized for sensor applications. We have succeeded to develop a simple, reproducible fabrication process to grow individual CNTs and CNT-networks directly within the specified device area. No tedious manual manipulation and alignment of the CNTs is necessary. Electrical results of the fabricated fully functional CNTFETs are presented and the use of these devices as single-walled CNT-based field-effect controlled sensors for virus detection is discussed.