International Conference on Computing Communication and Security 2015
04.-06.12.2015, Pointe aux Piments, Mauritius
Computation beyond Moore's Law: Adaptive field-effect devices for reconfigurable logic and hardware-based neural networks
Abstract – The success of integrated silicon technology is based on the down-scaling of minimum feature sizes of silicon field-effect devices (MOSFETs) in a complementary circuit configuration (CMOS) according to Moore's Law. Reducing the feature size provides more components per chip and higher speed. However, this continuous miniaturization of MOSFETs will come to an end as CMOS scaling will soon approach atomic dimensions. To take computation beyond Moore's Law requires breaking at least with two major paradigms: (1) High computing performance is directly related to high switching speeds of the single device and (2), the separation of memory and computing. In this work we report on a novel adaptive nanowire field-effect transistor (a-NWFET) architecture which provides a release from paradigms (1) as well as (2). The fabricated a-NWFETs are originally ambipolar nanowire devices, using midgap Schottky-barrier contacts as source and drain (S/D) electrodes. The final unipolar a-NWFET device type (i.e. PMOS or NMOS) can be created by applying an electric bias at the back-gate. The ability to select the transistor type by the application of an electrical signal to the back-gate adds to the versatility of the device concept, where the two CMOS devices are interchangeable immediately. A simple and versatile device structure for logic and intrinsic memory applications with the potential to realize novel reconfigurable logic architectures and hardware-based neural networks will be presented.
Design & Technology of Integrated Systems 2015
21.-23.04.2015, Naples, Italy
D. Noll, U. Schwalke
Silicon CMOS compatible in situ CCVD growth of graphene on silicon nitride
Abstract – In this paper we report on the possibility of the silicon CMOS compatible fabrication of graphene ﬁeld effect transistors on a silicon nitride high-k dielectric. For this purpose the catalytic chemical vapor deposition, which has already been approved to work on SiO2 surfaces, is used to grow the graphene. First electrical results indicate a bilayer graphene with an on/off current ratio of 103 to 104, which can be achieved with lower threshold voltages. A greater on/off current ratio may be possible, as the off current is determined through gate leakage current.
Member of the Technical Programm Committe: Prof. Dr. U. Schwalke
Antrittsvortrag von Ilke Ercan
Termin: Freitag, 17.04.2015, 14:00 c.t.
Ort: S2|17 103
Referent: PhD Ilke Ercan
Heat dissipation bounds for nanocomputing: Methodology and applications
Heat dissipation and power consumption are the critical challenges facing the realization of emerging nanocomputing technologies. There are different components of this dissipation, and a part of it comes from the unavoidable cost of implementing logically irreversible operations. This stems from the fact that information is physical and manipulating it irreversibly requires energy. The unavoidable dissipative cost of losing information irreversibly fixes the fundamental limit on the minimum energy cost for computational strategies that utilize ubiquitous irreversible information processing.
A relation between the amount of irreversible information loss in a circuit and the associated energy dissipation was formulated by Landauer's Principle in a technology-independent form. In a computing circuit, in addition to the information-theoretic dissipation, other physical processes that take place in association with irreversible information loss may also have an unavoidable thermodynamic cost that originates from the structure and operation of the circuit. In conventional CMOS circuits such unavoidable costs constitute only a minute fraction of the total power budget, however, in nanocircuits, it may be of critical significance due to the high device density and operation speeds required. The lower bounds on energy, when obtained by considering the irreversible information cost as well as unavoidable costs associated with the operation of the underlying computing paradigm, may provide insight into the fundamental limitations of emerging technologies. This motivates us to study the problem of determining heat dissipation of computation in a way that reveals fundamental lower bounds on the energy cost for circuits realized in new computing paradigms.
In this talk, I present a physical-information-theoretic methodology proposed to obtain such bounds for the minimum energy requirements of computation for concrete circuits realized within specific paradigms, and demonstrate its application via prominent nanocomputing proposals. I discuss the unavoidable heat dissipation problem and emphasize the significance of limitations it imposes on emerging technologies, present the methodology developed to obtain the lower bounds on the unavoidable dissipation cost of computation and demonstrate our methodology via its application to various non-transistor-based (e.g. QCA) and transistor-based (e.g. NASIC) nanocomputing circuits. I also employ two CMOS circuits, in order to provide further insights into the application of our methodology by using this well-known conventional paradigm. I expand this methodology to modularize the dissipation analysis for QCA and NASIC paradigms, and discuss prospects for automation. Finally, I comment on the role of fundamental lower bounds in technology assessment for determining the trends in nanoelectronic computing.