News-Archiv 2013

International Design and Test Symposium 2013

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16.-18.12.2013, Marrakesh, Morocco

U. Schwalke, F. Wessely, T. Krauss
Simulation and Experimental Verification: Dopant-free Si-Nanowire CMOS Technology on Silicon-on-Insulator Material

Abstract – In CMOS technology, NMOS- and PMOS-FETs are hardware defined by choosing the appropriate doping of source (S) and drain (D) junctions with respect to the substrate. However, in this work we report on a novel CMOS multi-gate (MG) nanowire field-effect transistor (NWFET) architecture on silicon-on-insulator (SOI) material which is virtually free of doping. The MG-NWFETs are originally ambipolar nanowire devices with midgap Schottky-barriers serving as S/D contacts. A tri-gate structure is used as front-gate for current control across the NWFET whereas a planar back-gate is used to select the desired unipolar device type (i.e. NMOS or PMOS) via field-induced accumulation of electrons or holes, respectively. Both, logic and memory devices can be realized with the same simple nanowire structure. By means of 2D and 3D device simulation and subsequent experimental verification the potential of this novel reconfigurable device and circuit architecture will be demonstrated.

Further contributions

Panel session with Prof. Udo Schwalke:
Nano Electronics Design: Challenges and Opportunities

Embedded Tutorial by Prof. Udo Schwalke:
The Future of Nanoelectronics is Black: From Silicon to Carbon?

Details: program ovverview / full program

Africon 2013

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09.-12.09.2013, Mauritius

U. Schwalke
The Future of Nanoelectronics is Black:
From Silicon to Hexagonal Carbon

Abstract – Silicon has been the ultimate semiconductor material in micro- and nanoelectronics for more than 50 years. However, the use of pure silicon based devices will come to an end when CMOS downscaling will soon reach its physical limits. In order to gain performance, new materials with high carrier mobility are required. Hexagonal carbon seems to be a promising alternative to build high performance electronic devices. For example, carbon nanotube field-effect transistors (CNTFETs) can be used as active devices in integrated circuits and as memory cells. More recently, another hexagonal carbon modification became the focus of scientific attention: graphene. Just a few years after the Nobel Prize Award in 2010 for the graphene discovery, graphene-based transistors are emerging as other potential candidates to extend and eventually replace the traditional silicon MOSFET. This contribution will give a brief overview on the recent progress achieved in carbon-based nanoelectronics.

Session Chair: Prof. Dr. Udo Schwalke
(Session on Wednesday 11th, September – „Sustainable Engineering, Energy and Environment“)

Artikel im Dieburger Anzeiger und in der Offenbach-Post

Artikel im Dieburger Anzeiger

In der Ausgabe vom 19. August des Dieburger Anzeigers und in der Ausgabe vom 23. August 2013 der Offenbach-Post sind jeweils Artikel zur Auszeichnung von Pia Juliane Wessely mit dem Best Paper Award der DTIS 2013 erschienen.

(Mit freundlicher Genehmigung von Jens Dörr, Journalist und Pressefotograf, www.jensdoerr.com)

E-MRS 2013 Spring Meeting

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27.-30.05.2012, Strasbourg, France

P.J. Wessely, U. Schwalke
Bilayer Graphene Transistors: Silicon CMOS Compatible Processing for Applications in Nanoelectronics

Abstract – We invented a method to fabricate graphene field effect transistors (GFETs) on oxidized silicon wafers in a Silicon CMOS compatible process. The graphene layers needed are grown in-situ in a transfer-free catalytic chemical vapor deposition (CCVD) process directly on silicon dioxide. Depending on the process parameters the fabrication of single, double or multi-layer graphene FETs (GFETs) is possible. The produced graphene layers has been characterized by SEM, TEM, TEM-lattice analysis as well as Raman-Spectroscopy. Directly after growth, the fabricated GFETs are electrically functional and can be electrically characterised via the catalyst metals used as contact electrodes. The fabricated bilayer graphene FETs (BiLGFETs) exhibit unipolar p-type MOSFET behavior. The on/off current-ratio of up to 107 of the fabricated BiLGFETs at room temperature allows their use in digital logic applications. Furthermore, a stable hysteresis of the GFETs enables their use as memory devices without the need of storage capacitors and therefore very high memory device densities are possible. The small decrease of the on/off current-ratio at temperatures of 200 °C of only one order of magnitude makes them ideal candidates for high-temperature applications, where low leakage currents are required so that cooling efforts can be reduced. The whole fabrication process is fully Si-CMOS compatible, enabling the use of hybrid silicon/graphene electronics.

223rd Meeting of the Electrochemical Society

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12.-16.05.2013, Toronto, Ontario, Canada

The ISTN participates with two presentations in the 223rd Meeting of the Electrochemical Society.


U. Schwalke, F. Wessely, T. Krauss
Dopant-free CMOS on SOI: Multi-Gate Si-Nanowire Transistors for Logic and Memory Applications

Abstract – In CMOS technology, NMOS- and PMOS-FETs are hardware defined by choosing the appropriate doping of the source (S) and drain (D) junctions with respect to the substrate. However, in this work we report on a novel CMOS multi-gate (MG) nanowire field-effect transistor (NWFET) architecture on silicon-on-insulator (SOI) material which is free of doping. The fabricated MG-NWFETs are originally unipolar nanowire devices with midgap Schottky-barriers for S/D contacts. A tri-gate structure serves as front-gate for current control across the NWFET whereas the back-gate is used to select the desired device type (i.e. NMOS or PMOS) via field-induced accumulation of electrons or holes, respectively.


P.J. Wessely, U. Schwalke
Transfer-free Bilayer Graphene FETs: Application as Memory Devices

Abstract – In this paper we report on the application of in-situ CCVD grown bilayer graphene transistors (BiLGFETs) as memory devices. By means of catalytic chemical vapor deposition (CCVD) the BiLGFETs are realized directly on oxidized silicon substrate without transfer. These BiLGFETs possess unipolar p-type device characteristics with a high on/off-current ratio between 1•105 and 1•107 at room temperature. The hysteresis of BiLGFETs depends on the cycling range of the applied backgate voltage while the sub-threshold slope is uniform for varied temperatures and varied cycling ranges of the backgate voltage. Based on the observed properties of BiLGFETs it is possible to use BiLGFETS as memory devices.

Design & Technology of Integrated Systems 2013

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Best Paper Award - DTIS 2013
IEEE DTIS 2013 – Best Paper Award

26.-28.03.2013, Abu Dhabi, United Arab Emirates

The ISTN participates with two presentations in this year's International Conference on Design & Technology of Integrated Systems in the Nanoscale Era.

Session 1A: Emerging Devices and Applications


P.J. Wessely, U. Schwalke
Transfer-Free Grown Bilayer Graphene Memory Devices

Awarded with the „Best Paper Award“ of 2013

Abstract – In this paper we report on the application of in-situ CCVD grown bilayer graphene transistors (BiLGFETs) as memory devices, grown in a Silicon-CMOS compatible fabrication process. By means of catalytic chemical vapor deposition (CCVD) the BiLGFETs are realized directly on oxidized silicon substrate without transfer. These BiLGFETs possess unipolar p-type device characteristics with a high on/off-current ratio between 1•105 and 1•107 at room temperature. The hysteresis of BiLGFETs depends on the cycling range of the applied backgate voltage while the sub-threshold slope is uniform for varied temperatures and varied cycling ranges of the backgate voltage. Based on the observed properties of BiLGFETs it is possible to use BiLGFETS as memory devices.


M. Keyn, U. Schwalke
Multi-CNTFETs for Power Device Applications: Investigation of CCVD Grown CNTs by Means of Atomic Force Microscopy

Abstract – In this work we use atomic force microscopy to explore carbon nanotubes (CNTs) which are grown by means of catalytic chemical vapor deposition (CCVD). The used process can be utilized to fabricate hundreds of carbon nanotube field-effect transistors (CNTFETs) for logic as well as for power device applications. The application type is selected through specially patterned source/drain contacts which either allow only one linking CNT (logic applications) or provide large scale parallelization of numerous CNTs (“multi-CNTFET”) for power device applications.


Member of the Programm Committe: Prof. Dr. U. Schwalke